What is RTL Verification Updates?
Working for Siemens EDA (formerly Mentor Graphics) and being the author of Python for RTL Verification, The UVM Primer, and FPGA Verification, I see a lot of cool ideas for verifying RTL. I’ve never had a good way to share them until now.
You can get ideas in your inbox by subscribing to this free substack.
Subscribe to RTL Verification Update
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Engineer == Author